1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a lateral power MOSFET.
2. Description of Prior Art
The development of single chip processes for integrating power switches with control circuitry is a major trend in the field of power IC development. The LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs. The LDMOS process involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction. Since the lateral MOSFET is manufactured using a typical IC process, the control circuit and the lateral power MOSFET can be integrated onto a monolithic power IC. An LDMOS process using a reduced surface electric field (RESURF) technique with a low thickness EPI or N-well can achieve a high voltage with low on-resistance.
Recently, many LDMOS designs have been proposed for integrating control circuitry with power switches. Among these, high-voltage LDMOS transistors are described in the following prior arts: “High Voltage MOS Transistors” by Klas H. Eklund, U.S. Pat. No. 4,811,075; “Narrow Radius Tips for High Voltage Semiconductor Devices with Interdigitated Source and Drain Electrodes” by Vladimir Rumennik and Robert W. Busse, U.S. Pat. No. 5,258,636; and “High Breakdown Voltage Semiconductor Device” by Masaaki Noda, U.S. Pat. No. 6,617,652 B2.
High-voltage and low-resistance LDMOS are disclosed in the following patents: “High Voltage MOS Transistor with a Low On-Resistance” by Klas H. Eklind, U.S. Pat. No. 5,313,082; “MIS Semiconductor Device with Low On Resistance and High Breakdown Voltage” by Gen Tada, Akio Kitamura, Masaru Saito, and Naoto Fujishima, U.S. Pat. No. 6,525,390 B2; and “High-voltage Transistor with Multi-layer Conductor Region” by Vladimir Rumennik, Donald R. Disney, and Janardhanan S. Ajit, U.S. Pat. No. 6,570,219 B2.
One drawback of all of these prior arts is that the electric field maximum of the transistor occurs near the silicon surface. This may cause reliability problems during high-temperature operation. Another drawback of these prior-art transistors is non-isolated source structure. With monolithic designs, non-isolated transistor current could flow around the substrate and generate noise interference in the control circuit.
To overcome these drawbacks, the present invention proposes a split well structure for spreading the electric field into the body of the transistor. This can substantially improve the reliability of the transistor. Additionally, an isolated transistor structure is proposed to control a transistor current flow.